Conference
A. P. Sawant, R. Raina, C. G. Healey
3rd International Symposium on Visual Computing (ISVC '07), 2007, pp. 711-720
3rd International Symposium on Visual Computing (ISVC '07), 2007, pp. 711-720
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APA
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Sawant, A. P., Raina, R., & Healey, C. G. (2007). ChipViz : Visualizing Memory Chip Test Data. In 3rd International Symposium on Visual Computing (ISVC '07) (pp. 711–720).
Chicago/Turabian
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Sawant, A. P., R. Raina, and C. G. Healey. “ChipViz : Visualizing Memory Chip Test Data.” In 3rd International Symposium on Visual Computing (ISVC '07), 711–720, 2007.
MLA
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Sawant, A. P., et al. “ChipViz : Visualizing Memory Chip Test Data.” 3rd International Symposium on Visual Computing (ISVC '07), 2007, pp. 711–20.
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@conference{a2007a,
title = {ChipViz : Visualizing Memory Chip Test Data},
year = {2007},
pages = {711-720},
author = {Sawant, A. P. and Raina, R. and Healey, C. G.},
booktitle = {3rd International Symposium on Visual Computing (ISVC '07)}
}
Abstract
This paper presents a technique that allows test engineers to visually analyze and explore within memory chip test data. We represent the test results from a generation of chips along a traditional grid and a spiral. We also show correspondences in the test results across multiple generations of memory chips. We use simple geometric “glyphs” that vary their spatial placement, color, and texture properties to represent the critical attribute values of a test. When shown together, the glyphs form visual patterns that support exploration, facilitate discovery of data characteristics, relationships, and highlight trends and exceptions in the test data that are often difficult to identify with existing statistical tools.
